By Philip M. Sailer, David R. Kaeli; Morgan Kaufmann, 1996, ISBN 1558603719, 1st edition. Definitive work on DLX instructions. Information and abstract. ACM Portal.

Documents DLX implementation by Microsystems Prototyping Laboratory (MPL), MSU Engineering Research Center; used as design driver to help validate standard cell libraries.

Tables of instructions, categorized, as PDF slides. By Guy Even, Tel Aviv University.

DLXOS information needed for programming, from introductory course on OSs.

Simple DLX implementation using VHDL; diagrams, descriptions, links.

Master's Thesis: Design and Evaluation of a RISC Processor with a Tomasulo Scheduler. Uses DLX. HTML, PS, GZ, PDF.

Introductory HTML slide show.

Class overview with tables (instruction format, set) and diagrams (timing), some other information. By Ethan Miller, University of Maryland.

VHDL model of processor; most instructions use 5 clock cycles to run, jumps use 3, floating point timing not fully accurate because fp instructions also take 5 cycles to run; description, download.

PDF slides, mostly code.