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Ashling and Embecosm to Accelerate RISC-V Vector QEMU Emulation…
May 24, 2024 Limerick, Ireland. Ashling and their partner Embecosm announced today that they are working with the RISE (RISC-V Software Ecosystem) Project to optimize RISC-V vector instructions emulation for QEMU the open-source emulator. Our joint goal is to ensure that RISC-V vector instructions powered binaries run at rocket speed under QEMU by mapping the RISC‑V vector instructions to the best hardware equivalents on the host, leveraging up to 256-bit SIMD vectors for maximum performance.
Ashling will be attending the Embedded World Conference in Nuremberg (April-9 to 11) followed by the European RISC-V Summit in Munich (June-24 to 28)…
April 4, 2024 Limerick, Ireland. Latest Ashling news including details on the upcoming Embedded World Conference in Nuremberg and RISC-V Summit in Munich where we’ll be showcasing our latest embedded development tools & solutions…
Synopsys ARC-V RISC-V ISA based Processors are coming and Ashling announce full tools support including RiscFree™ C/C++ SDK support…
November 7th, 2023, RISC-V Summit, Santa Clara, Silicon Valley, California, USA. Ashling today announced support for the Synopsys ARC-V RISC-V ISA compliant Processor family…