Develops software which aids your ASIC flow from design through verification.

The Spyglass suite of tools uses predictive analysis technique that performs structural analysis on Verilog and VHDL RTL to detect design problems in SoCs and ASICs.

Breakthrough in logic verification. Funded by very experienced people from EDA

A merging of design software companies, which creates a complete PC based design environment. This includes everything from ASIC design to PCB design.

An Open Source interactive simulator frontend for Verilog and VHDL circuit simulation.

Developers of innovative design verification and coverage software.

Offers design services in the area of FPGA design, Embedded Design, PCB Design and ASIC design.

Tools for FPGA design and testing, evaluation boards for FPGA prototyping, hardware and system design consulting.